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quad parametric measurement unit with integrated 16-bit level setting dacs preliminary technical data ad5522 rev.prm information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features quad parametric measurement unit fv, fi, fn, mv, mi functions 4 programmable current ranges (internal r sense ) 5ua, 20ua, 200ua and 2ma 1 programmable current range up to 64ma (external r sense ) 22.5 v fv range with asymmetrical operation integrated 16-bit dacs provide programmable levels offset and gain correction on chip low capacitance outputs suited to relay less systems on-chip comparators per channel fi voltage clamps & fv current clamps guard drive amplifier system pmu connections programmable temperature shutdown feature spi/microwire/dsp & lvds compatible interfaces compact 80 lead tqfp package with exposed pad (top or bottom) applications automatic test equipment (ate) per pin parametric measurement unit continuity & leakage testing device power supply instrumentation smu (source measure unit) precision measurement product overview the ad5522 is a high performance, highly integrated parametric measurement unit consisting of four independent channels. each ppmu channel includes five, 16-bit, voltage out dacs setting the programmable inputs levels for the force voltage input, clamp and comparator inputs (high and low). five programmable force and measure current ranges are available ranging from 5a to 64ma. four of these ranges use on chip sense resistors, while a high current range up to 64ma is available per channel using off chip sense resistors. currents in excess of 64ma require an external amplifier. low capacitance dut connections (foh, ext foh) ensure the device is suited to relay less test systems. the pmu functions are controlled via a simple three wire serial interface compatible with spi/qspi/microwire and dsp interface standards. interface clocks of 50mhz allow fast updating of modes. lvds (low voltage differential signaling) interface protocol at 100mhz is also supported. comparator outputs are provided per channel for device go no-go testing and characterization. control registers provide easy way of changing force or measure conditions, dac levels and selected current ranges. sdo (serial data out) allows the user to readback information for diagnostic purposes. 16 16 16 dutgnd measvh (0-3) guard (0-3) cgalm sclk sync sdi sdo cpol0/ sclk cpol2 /cpo0 serial interface cpoh0/ sdi cpol1/ sync cpoh1/ sdo lvds/ spi reset busy 16 clamp & guard alarm cpoh2 /cpo1 cpol3 /cpo2 cpoh3 /cpo3 power on reset guardin (0-3)/ dutgnd ( 0-3 ) dut external rsense (currents up to 64ma) extmeasih(0-3) extmeasil(0-3) foh(0-3) extfoh(0-3) c ff (0-3) fin clh cll av ss (0-4) agnd (0-3) av dd (0-4) + - measout (0-3) x4 dgnd cph comparator c comp (0-3) load cpl internal range select (5ua, 20ua, 200ua, 2ma) - - - - - - + + + + + + rsense - - + + 16 16 16 16 temp sensor vref sys_force sys_sense dv cc 16 x1 reg creg mreg 16 16 16 16 16 16 16 16 16-bit fin dac x5 or x10 *2 x1 tmpalm agndx refgnd 16-bit clh dac 10k ? measout mux & gain x1/x0.2 x1 reg creg mreg x1 reg creg mreg 16 *2 16 16 16 16 x1 reg creg mreg *6 *6 offset dac 16-bit offset dac to all dac output amplifiers force amplifer measure current in amp 16-bit cll dac 16-bit cph dac 16-bit cpl dac agndx sw 1 sw 2 sw 3 sw 4 60 ? sw 6 sw 5 sw 9 sw 8 sw 7 sw 10 sw 11 measure voltage in amp temp sensor to measout mux sw 12 x1 reg creg mreg *6 x2 reg x2 reg x2 reg *6 x2 reg x2 reg *6 *6 *2 *2 agnd en 1k ? guard amp sw 13 sw 14 agndx 10k ? sw 15 sw 16 dutgnd offset dac bias to center irange figure 1. functional block diagram
ad5522 preliminary technical data rev. prm | page 2 of 48 table of contents features..................................................................................................................... 1 revision history...................................................................................................... 2 specifications ........................................................................................................... 4 table 2. timing characteristics .................................................................... 9 absolute maximum ratings................................................................................ 12 thermal resi stance.......................................................................................... 12 esd caution ..................................................................................................... 12 pin configuration and function descriptions................................................. 13 terminology.................................................................................................. 16 functional description ........................................................................................ 17 force amplifier ................................................................................................ 19 comparators ..................................................................................................... 19 clamps ............................................................................................................... 19 current range selection.................................................................................. 20 high current ranges........................................................................................ 20 device under test ground (dutgnd) ........................................................ 20 guard amplifer ................................................................................................. 21 compensation capacitors .............................................................................. 21 system force sense switches.......................................................................... 22 temperature sensor......................................................................................... 22 measure output (measout) ...................................................................... 22 dac levels............................................................................................................. 23 offset dac........................................................................................................ 23 offset and gain registers ................................................................................ 23 cached x2 registers .......................................................................................... 23 v ref ..................................................................................................................... 24 reference selection.......................................................................................... 24 calibration ........................................................................................................ 25 system level calibration ................................................................................ 25 force voltage, fv ............................................................................................. 26 force current, fi.............................................................................................. 27 spi interface .............................................................................................. 28 lvds interface.......................................................................................... 28 serial interface write mode ........................................................................... 28 reset function............................................................................................... 28 busy and load function ............................................................................ 28 register update rates...................................................................................... 29 register selection............................................................................................. 30 write system control register....................................................................... 31 write pmu register ........................................................................................ 33 write dac register ......................................................................................... 35 read registers................................................................................................... 37 readback of system control register........................................................... 38 readback of pmu register............................................................................. 39 readback of comparator status register..................................................... 39 readback of alarm status register ............................................................... 40 readback of dac register ............................................................................. 40 power on default ............................................................................................ 41 setting up the device on power on ................................................................ 42 changing modes .............................................................................................. 42 required external components ...................................................................... 43 typical applicatio n for the ad5522 ............................................................. 45 outline dimensions ............................................................................................. 46 ordering guide ................................................................................................ 47 notes ....................................................................................................................... 48 revision history rev prm, 12 th march C update to specification pages, addition of typical plots, general update of all sections of datasheet. update of ad552 2 models. .
preliminary technical data ad5522 rev. prm | page 3 of 48 dutgnd measvh 0 guard 0 cpol0/ sclk cpoh0/ sdi guardin 0/ dutgnd 0 dut external rsense (currents up to 64ma) extmeasih 0 extmeasil 0 foh 0 extfoh 0 c ff 0 fin clh cll av ss (0-4) agnd av dd (0-4) + - measout 0 ch0 dgnd cph comparator c comp 0 internal range select (5ua, 20ua, 200ua, 2ma) - - - - - - + + + + + + rsense - + vref sys_force sys_sense dv cc x5 or x10 x1 agnd offset dac bias to center irange 10k ? force amplifer measure current in amp sw 1 sw 2 sw 3 sw 5 sw 6 sw 4 sw 9 sw 8 sw 7 measure voltage in amp cgalm sclk sync sdi sdo cpol2/cpo0 serial interface cpol1/ sync cpoh1/ sdo reset busy 16 clamp & guard alarm cpoh2/cpo1 cpol3 /cpo2 cpoh3 /cpo3 power on reset temp sensor tmpalm 16 16-bit offset dac to all dac output amplifiers to measout mux dutgnd measvh 3 guard 3 guardin 3/ dutgnd 3 dut external rsense (currents up to 64ma) extmeasih 3 extmeasil 3 foh 3 extfoh 3 c ff 3 fin clh cll + - measout 3 cph comparator internal range select (5ua, 20ua, 200ua, 2ma) - - - - - - + + + + + + rsense - + x5 or x10 x1 10k ? force amplifer measure current in amp sw 1 sw 2 sw 3 sw 5 sw 6 sw 4 sw 9 sw 8 sw 7 measure voltage in amp ch1 ch3 ch2 c comp 3 measvh 2 extmeasil 2 foh 2 extfoh 2 c ff 2 extmeasih 2 guard 2 guardin 2/dutgnd 2 measvh 1 extmeasil 1 foh 1 extfoh 1 c ff 1 extmeasih 1 guard 1 guardin 1/dutgnd 1 measout 1 c comp 1 measout 2 c comp 2 dutgnd dutgnd 16 16 16 cpl - + 16 16 16 16 16 x1 reg creg mreg 16 16 16 16 16 16 16 16 16-bit fin dac *2 16-bit clh dac measout mux & gain x1/x0.2 x1 reg creg mreg x1 reg creg mreg *2 16 16 16 16 x1 reg creg mreg *6 offset dac 16-bit cll dac 16-bit cph dac 16-bit cpl dac sw 10 sw 11 temp sensor sw 12 x1 reg creg mreg *6 x2 reg x2 reg 16 16 16 cpl - + 16 16 16 16 16 x1 reg creg mreg 16 16 16 16 16 16 16 16 16-bit fin dac *2 16-bit clh dac measout mux & gain x1/x0.2 x1 reg creg mreg x1 reg creg mreg *2 16 16 16 16 x1 reg creg mreg *6 offset dac 16-bit cll dac 16-bit cph dac 16-bit cpl dac sw 10 sw 11 temp sensor sw 12 x1 reg creg mreg *6 x2 reg x2 reg x2 reg *6 x2 reg *6 x2 reg *6 *2 *2 x2 reg *6 x2 reg *6 x2 reg *6 *2 *2 agnd agnd en mux mux lvds/ spi load agnd agnd agnd refgnd agnd agnd en sw 13 sw 13 guard amp sw 14 guard amp sw 14 agndx 10k ? sw 15 sw 16 sw 16 agnd 10k ? sw 15 dutgnd agnd 10k ? sw 15a offset dac bias to center irange figure 2. detailed block diagram
ad5522 preliminary technical data rev. prm | page 4 of 48 specifications table 1. av dd 10v, av ss ? 5v, |av dd C av ss | 20v and 33v, dv cc = 2.3v to 5.25v, v ref =5v, gain (m), offset (c) and dac offset registers at default values (t j = +25 to +90 o c, max specs unless otherwise noted.) parameter min typ 1 max units test conditions/comments force voltage foh output voltage range av ss +4 av dd -4 v all current ranges from foh at full scale current. includes 1v dropped across sense resistor extfoh output voltage range av ss +3 av dd -3 v external high current range at full scale current. does not include 1v dropped across sense resistor output voltage span 22.5 v offset error -100 100 mv me asured at midscale code, 0v. prior to calibration. offset error tempco 2 100 v/ o c gain error -0.5 0.5 % prior to calibration. gain error tempco 2 10 ppm/ o c linearity error -0.02 0.02 % fsr fsr = fullscale range. 10 v range, gain and offset errors calibrated out. short circuit current limit 2 -120 120 ma on 64ma range. -10 10 ma in all other ranges. measure current measure = (idut x rsense x gain) offset error -1 1 % v(rsense)= 1v, measured with zero current flowing. offset error tempco 2 10 v/ o c gain error -1 1 % instrumentation amp gain = 5 or 10 gain error tempco 2 25 ppm/ o c linearity error -0.01 0.01 % fscr offset and gain errors calibrated out output voltage span 2 22.5 v cm error -0.005 0.005 %fsvr/v % of fs change at measure output per v change in dut voltage measure current ranges 5 a set using internal sense resistor 20 a set using internal sense resistor 200 a set using in ternal sense resistor 2 ma set using internal sense resistor up to 64 ma set using external sense resistor, internal amplifier can drive to 64ma force current voltage compliance, foh av ss +4 av dd -4 v voltage compliance, extfoh av ss +3 av dd -3 v offset error -2 2 %fscr measured at midscale code, 0v. prior to calibration. offset error tempco 2 10 ppm fs/ o c gain error -0.5 0.5 % prior to calibration. gain error tempco 2 25 ppm/ o c linearity error -0.02 0.02 % fscr cm error -0.005 0.005 %fscr/v % of fs change at measure output per v change in dut voltage force current ranges 5 a se t using internal se nse resistor, 200k? 20 a set using in ternal sense resistor, 50k? 200 a set using in ternal sense resistor, 5k? 2 ma set using in ternal sense resistor, 500? up to 64 ma set using external sense resistor, internal amplifier can drive to 64ma
preliminary technical data ad5522 rev. prm | page 5 of 48 measure voltage measure voltage range av dd -4 v av ss +4 v offset error -10 10 mv gain = 1, measured at 0v offset error -40 40 mv gain = 0.2, measured at 0v offset error tempco 2 10 v/ o c gain error -0.5 0.5 % fsr gain = 1 gain error -0.5 0.5 % fsr gain = 0.2 gain error tempco 2 10 ppm/ o c linearity error -0.01 0.01 % fsr comparator comparator span 22.5 v offset error -10 1 10 mv propagation delay 2 0.25 s voltage clamps clamp span 22.5 v positive clamp accuracy 150 mv negative clamp accuracy -150 mv recovery time 2 0.5 1.5 s activation time 2 1.5 3 s current clamps clamp accuracy progd clamp value programmed clamp value +15 % of fsc range clamp current scales with selected range recovery time 2 0.5 1.5 s activation time 2 1.5 3 s foh, extfoh, extmeasil, extmeasih, cff pin capacitance 2 10 pf leakage current -3 3 na on or off switch leakage leakage current tempco 2 0.1 na/ o c measvh pin capacitance 2 3 pf leakage/bias current -3 3 na leakage current tempco 2 0.1 na/ o c sys_sense sys_sense connected, force amplifier inhibited pin capacitance 2 3 pf sys_sense impedance 1 1.3 k? leakage current -3 3 na leakage current tempco 2 0.1 na/ o c sys_force sys_force connected, force amplifier inhibited pin capacitance 2 6 pf sys_force impedance 60 80 ? leakage current -3 3 na leakage current tempco 2 0.1 na/ o c combined leakage at dut includes foh, measvh, sys_sense, sys_force, extmeasil leakage current -15 15 na leakage current tempco 2 0.5 na/ o c typ dutgnd voltage range -500 500 mv leakage current -1 1 a
ad5522 preliminary technical data rev. prm | page 6 of 48 measure output (measout) with respect to agnd measure output voltage span 22.5 v software programmable output range measure pin output impedance 100 ? output leakage current -3 3 na with sw12 off output capacitance 2 15 pf max load capacitance 2 1 f output current drive 2 2 ma short circuit current 2 -10 10 ma measout slew rate 2 2 v/s measout enable time 2 150 320 ns closing sw12, measured from busy rising edge. measout disable time 2 400 1100 ns opening sw12, measured from busy rising edge. measout mi to mv switching time 2 200 ns measured from busy rising edge. guard output guard output voltage span 22.5 v guard output offset -10 10 mv short circuit current 2 -10 10 ma max load capacitance 2 1000 nf guard output impedance 100 ? slew rate 2 5 v/s c load = 10 pf alarm activation time 2 200 s alarm delayed to eliminate false alarms. force amplifier slew rate 2 0.4 v/us ccomp=100pf, cff=220pf, cload=200pf gain bandwidth 2 1.3 mhz ccomp=100pf, cff=220pf, cload=200pf max stable load capacitance 2 10,000 pf c comp = 100pf. larger load cap requires larger c comp 100 nf c comp = 1nf. larger load cap requires larger c comp fv settling time to 0.05% of fs mid scale to full scale change, measured from /sync rising edge, clamps on 64ma range 2 17 40 s ccomp=100pf, cff=220pf, cload=200pf 2ma range 2 17 40 s ccomp=100pf, cff=220pf, cload=200pf 200a range 2 32 80 s ccomp=100pf, cff=220pf, cload=200pf 20a range 2 tbd 80 s ccomp=100pf, cff=220pf, cload=200pf 5a range 2 tbd 300 s ccomp=100pf, cff=220pf, cload=200pf mi settling time to 0.05% of fs mid scale to full scale change, measured from /sync rising edge, clamps on 64ma range 2 17 40 s ccomp=100pf, cff=220pf, cload=200pf 2ma range 2 18 40 s ccomp=100pf, cff=220pf, cload=200pf 200a range 2 40 80 s ccomp=100pf, cff=220pf, cload=200pf 20a range 2 tbd tbd s ccomp=100pf, cff=220pf, cload=200pf 5a range 2 tbd tbd s ccomp=100pf, cff=220pf, cload=200pf fi settling time to 0.05% of fs mid scale to full scale change, measured from /sync rising edge, clamps on 64ma range 2 18 55 s ccomp=100pf, cload=200pf 2ma range 2 22 85 s ccomp=100pf, cload=200pf 200a range 2 45 120 s ccomp=100pf, cload=200pf 20a range 2 1000 tbd s ccomp=100pf, cload=200pf 5a range 2 2300 4000 s ccomp=100pf, cload=200pf mv settling time to .05% of fs mid scale to full scale change, measured from /sync rising edge, clamps on 64ma range 2 20 65 s ccomp=100pf, cload=200pf 2ma range 2 21 85 s ccomp=100pf, cload=200pf 200a range 2 50 120 s ccomp=100pf, cload=200pf 20a range 2 1000 tbd s ccomp=100pf, cload=200pf 5a range 2 2300 4000 s ccomp=100pf, cload=200pf
preliminary technical data ad5522 rev. prm | page 7 of 48 dac specifications resolution 16 bits voltage output span 2 22.5 v v ref =5v, within a range of -16.25 to 22.5v differential nonlinearity 2 -1 1 lsb guaranteed monotoni c by design over temperature. comparator dac dynamic specifications output voltage settling time 2 1.5 s 500mv change to ? lsb. slew rate 2 5.5 v/s digital-to-analog glitch energy 2 20 nv-s glitch impulse peak amplitude 2 10 mv reference input v ref dc input impedance 1 m? typically 100 m?. v ref input current -10 10 a per input. typically 30 na. v ref range 2 5 v die temperature sensor accuracy 7 c output voltage at 25c 1.5 v output scale factor 5 mv/c output voltage range 0 3 v interaction & crosstalk crosstalk (vm) 2 -0.01 0.01 % fsr all channels in fi mv mode, measure the voltage for one channel in the highest current force range, once when all three other channels are at fi = 0ma and once when they are at 2ma crosstalk (mi) 2 -0.01 0.01 % fsr all channels in fvmi mode, measure the current for one channel in the lowest current measure range, once when all three other channels are at fv = -10v and once when they are at +10v crosstalk within a channel 2 0.5 mv all channels in fvmi mode, one channel at midscale, measure the current for one channel in the lowest current range, for a change in comparator or clamp dac levels for that pmu. shorted dut crosstalk 2 tbd tbd s/c applied to one pmu channel, measure effect on other channels. spi interface logic logic inputs v ih , input high voltage 1.7/2.0 v (2.3 to 2. 7)/(2.7 to 5.25v) jedec compliant input levels v il , input low voltage 0.7/0.8 v (2.3 to 2. 7)/(2.7 to 5.25v) jedec compliant input levels i inh , i inl , input current -1 1 a c in , input capacitance 2 10 pf cmos logic outputs sdo, cpox v oh , output high voltage dv cc C 0.4 v v ol , output low voltage 0.4 v i ol = 500 a tristate leakage current -1 1 a output capacitance 2 10 pf open drain logic outputs busy , tmpalm, cgalm v ol , output low voltage 0.4 v i ol = 500 a, c l = 50pf, r pullup = 1k? output capacitance 2 10 pf lvds interface logic logic inputs C reduced range link input voltage range 875 1575 mv input differential threshold -100 100 mv external termination resistance 80 100 120 ? differential input voltage 100 mv logic outputs C reduced range link output offset voltage 1200 mv output differential voltage 400 mv
ad5522 preliminary technical data rev. prm | page 8 of 48 noise performance nsd of measure voltage in-amp 290 nv/hz @ 1khz, measured at measout nsd of measure current in-amp 290 nv/hz @ 1khz, measured at measout nsd of force amplifier 300 nv /hz @ 1khz, measured at foh power supplies av dd 10 28 v | av dd C av ss | 33v av ss -5 -23 v dv cc 2.3 5.25 v ai dd 25 ma internal ranges (5a to 2ma), excluding load conditions ai ss -25 ma internal ranges (5a to 2ma), excluding load conditions ai dd 35 ma external range, excluding load conditions ai ss -35 ma external range, excluding load conditions di cc 3 ma max power dissipation 2 7 w power supply sensitivity 2 from dc to 1khz ?forced voltage/?av dd -75 db ?forced voltage/?av ss -75 db ?measured current/?av dd -75 db ?measured current/?av ss -75 db ?forced current/?av dd -75 db ?forced current/?av ss -75 db ?measured voltage/?av dd -75 db ?measured voltage/?av ss -75 db ?forced voltage/?dv cc -90 db ?measured current/?dv cc -90 db ?forced voltage/?dv cc -90 db ?measured current/?dv cc -90 db 1 typical specifications are at 25c and nominal supply, 15.25v, unless otherwise noted. 2 guaranteed by design and characterization, not production tested. fv = force voltage, fi = force current, mv = measure voltage, mi = measure current fsr = full scale range, fscr = full scale current range, fs = full scale. specifications subject to change without notice.
preliminary technical data ad5522 rev. prm | page 9 of 48 table 2. timing characteristics av dd 10v, av ss ? 5v, |av dd C av ss | 20v and 33v, dv cc = 2.3v to 5.25v, v ref =5v (t j = +25 to +90 o c, max specs unless otherwise noted.) spi interface ( figure 5 and figure 6 ) parameter 1, 2, 3 limit at tmin, tmax unit description 595 ns min single channel write time t 1 20 ns min sclk cycle time. t 2 8 ns min sclk high time. t 3 8 ns min sclk low time. t 4 10 ns min sync falling edge to sclk falling edge setup time. t 5 15 ns min minimum sync high time. t 6 5 ns min 29th sclk falling edge to sync rising edge. t 7 5 ns min data setup time. t 8 4.5 ns min data hold time. t 9 3 30 ns max sync rising edge to busy falling edge. t 10 busy pulse width low 1 dac x1 1.25 s max busy pulse width low 2 dac x1 1.75 s max busy pulse width low 3 dac x1 2.25 s max busy pulse width low 4 dac x1 2.75 s max busy pulse width low other regs 270 ns max busy pulse width low, system control register/pmu register/m or c registers t 11 20 ns min 29 th slck falling edge to load falling edge t 12 20 ns min load pulse width low t 13 150 ns min busy rising edge to foh output response time t 14 0 ns min busy rising edge to load falling edge t 15 100 ns max load rising edge to foh output response time t 16 10 ns min reset pulse width low. t 17 300 s max reset time indicated by busy low. t 18 100 ns min minimum sync high time in readback mode. t 19 4, 5 25 ns max dv cc = 5v to 5.25v, sclk rising edge to sdo valid. 45 ns max dv cc = 3v to 3.7v, sclk rising edge to sdo valid 60 ns max dv cc = 2.3v to 3v, sclk rising edge to sdo valid lvds interface ( figure 7 ) parameter 1, 2, 3 limit at tmin, tmax unit description t 1 10 ns min sclk cycle time. t 2 4 ns min sclk pulse width high and low time. t 3 2 ns min sync to sclk setup time. t 4 2 ns min data setup time. t 5 2 ns min data hold time. t 6 2 ns min sclk to sync hold time. t 7 tbd ns min sclk rising edge to sdo valid. t 8 tbd ns min sync high time 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of v cc ) and timed from a voltage level of 1.2 v. 3 see figure 5 and figure 6 4 this is measured with load circuit of figure 4 5 sdo output gets slower with lower dv cc supply and may require use of slower sclk.
ad5522 preliminary technical data rev. prm | page 10 of 48 to output pin v cc r l 2.2k ? c l 50pf v ol 200a 200a 50pf c l i ol i ol v oh (min)-v ol (max) 2 to output pin figure 3.. load circuit for cgalm , tmpalm figure 4. load circuit for sdo, busy timing diagram sclk sync sdi busy reset 1 2 t 1 t 3 t 2 29 t 5 t 4 t 6 t 7 t 8 t 9 db28 db0 24 t 10 t 16 t 17 busy 1 load active during busy 2 load active after busy load 1 foh 1 load 2 foh 2 t 11 t 12 t 13 t 14 t 12 t 15 figure 5. spi write timing (write word contains 29 bits)
preliminary technical data ad5522 rev. prm | page 11 of 48 sclk sync sdi sdo 29 58 db28 db0 db23/ db28 db0 db0 input word specifies register to be read undefined nop condition selected register data clocked out t 18 t 19 db23/ db28 figure 6. spi read timing (readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges) sync sync sclk sdi sdi sclk msb d28 lsb d0 t6 t1 t2 t3 t4 t5 sdo lsb d0 msb d23/d28 t7 selected register data clock out undefined msb db23/ db28 lsb db0 sdo t 8 figure 7. lvds read and write timing, (readb ack word contains 24 bits and can be cloc ked out with a minimum of 24 clock edges)
ad5522 preliminary technical data rev. prm | page 12 of 48 absolute maximum ratings table 3. ad5522 absolute maximum ratings parameter rating supply voltage av dd to av ss 34v av dd to agnd -0.3v to 34v av ss to agnd 0.3v to -34v v ref to agnd -0.3 v, +7v dutgnd to agnd av dd +0.3v to av ss -0.3v refgnd to agnd av dd +0.3v to av ss -0.3v dv cc to dgnd - 0.3v to 7v agnd to dgnd - 0.3v to +0.3v digital inputs to dgnd - 0.3v to dv cc +0.3v analog inputs to agnd av ss - 0.3v to av dd +0.3v storage temperature C65c to +125c operating junction temperature +25 to +90c reflow soldering peak temperature 230c time at peak temperature 10s to 40s junction temperature 150c max stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance 3 thermal resistance values are specified for the worst-case conditions, i.e., specified for device soldered in circuit board for surface mount packages. table 4. thermal resistance (jedec 4 layer (1s2p) board) air flow (lfpm) 0 200 500 unit tqfp exposed pad down ja 22.3 17.2 15.1 c/w jc 4.8 c/w tqfp exposed pad up ja tbd tbd tbd c/w jc 2 c/w table 5. thermal resistance (jedec 4 layer (1s2p) board with cooling plate 4 at 45c, natural convection at 55c ambient) package thermals ja jc unit tqfp exposed pad down 5.4 4.8 c/w tqfp exposed pad up 3.0 2 c/w 3 simulated thermal information. 4 assumes perfect thermal contact between cooling plate and exposed paddle esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad5522 rev. prm | page 13 of 48 pin configuration and fu nction descriptions measvh1 cff3 ccomp3 agnd agnd guard1 av d d guardin1 /dutgnd1 foh1 extmeasih1 guardin3 /dutgnd3 extmeasih3 extmeasil3 foh3 av d d 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 cff1 extmeasil1 measvh3 ccomp1 guard3 c p o l 0 / s c l k b u s y a v s s e x t f o h 2 s c l k s d i s y n c d g n d c p o l 1 / s y n c s d o c p o h 1 / s d o l o a d d v c c c p o l 2 / c p o 0 c p o h 2 / c p o 1 c p o l 3 / c p o 2 c p o h 3 / c p o 3 a v s s e x t f o h 3 c p o h 0 / s d i 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 e x t f o h 1 d u t g n d 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 e x t f o h 0 a v s s r e s e t s y s _ s e n s e r e f g n d t m p a l m a g n d s y s _ f o r c e a v s s s p i / l v d s m e a s o u t 3 m e a s o u t 2 a v d d c g a l m a v s s m e a s o u t 1 v r e f m e a s o u t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 extmeasih2 guard0 extmeasil2 foh2 guard2 guardin2 /dutgnd2 measvh2 agnd agnd foh0 extmeasil0 measvh0 extmeasih0 avdd guardin0 /dutgnd0 av d d cff2 ccomp2 cff0 ccomp0 ad5522 top view exposedpadonbottom (not to scale) figure 8. pin configuration (exposed pad on bottom of package) table 6. pin function descriptions pin no. pin no. mnemonic description bottom top exposed pad the exposed pad is electrically connected to av ss . tqfp with exposed pad on bottom: for enhanced thermal, electrical and board level performance, the exposed paddle on the bottom of the package should be soldered to a corresponding thermal land paddle on the pcb. 22, 39, 62, 67, 79, 2, 14, 19, 42,59, av ss (0-4) negative analog supply voltage 1, 20, 41, 60, 74 7, 21, 40, 61, 80 av dd (0-4) positive analog supply voltage 33 48 load active low logic input used for synchronizing updates within one device or across a group of devices. if synchronization is not required, load may be tied low and updates to dac channels or pmu modes will happen as they are presented to the device. see the busy and load functions section for detailed information. 34 47 dv cc digital supply voltage 10, 11, 50, 51, 69 12, 30, 31, 70, 71 agnd analog ground, reference points for force and measure circuitry 30 51 dgnd digital ground reference point. 23 58 busy open drain active low input/output indicating the status of interface. 24 57 sclk clock input, active falling edge 25 56 cpol0/ sclk comparator output low in spi mode and sclk in lvds interface mode 26 55 cpoh0/ sdi comparator output high in spi mode and sdi in lvds interface mode 27 54 sdi serial data input 28 53 sync frame sync, active low 29 52 cpol1/ sync comparator output low in spi mode and sync in lvds interface mode 31 50 cpoh1/sdo comparator output high in spi mode and sdo in lvds interface mode
ad5522 preliminary technical data rev. prm | page 14 of 48 32 49 sdo serial data out, for re adback and diagnostic purposes 35 46 cpol2/cpo0 comparator output low, comparator window in lvds interface mode 36 45 cpoh2/cpo1 comparator output low, comparator window in lvds interface mode 37 44 cpol3/cpo2 comparator output low, comparator window in lvds interface mode 38 43 cpoh3/cpo3 comparator output low, comparator window in lvds interface mode 66, 65, 64, 63 15, 16, 17, 18 measout(0-3) multiplexed dut voltage/current sense output/temperature sensor voltage per channel, referenced to agnd. 68 13 sys_force external force signal inp ut, enables connection of system pmu. 70 11 sys_sense external sense signal output, enables connection of system pmu. 71 10 refgnd accurate analog reference input ground. 72 9 vref reference input for dac channels, 5v for specified performance. 75 6 spi /lvds interface select pin. logic low selects spi interface compatible mode, logic high selects lvds interface mode. in lvds mode the cpoh(0-3) pins default to differential interface pins. 76 5 cgalm cgalm is an open drain pin providing shared alarm information for guard amplifier and clamp circuitry. by default, this output pin is disabled. the system cont rol register allows user to enable this function and to set the open drain output as a latched output, or to configure either the guard or clamp function or both flagging the alarm pin. when this pin flags an alarm, the origins of the alarm may be determined by reading back the alarm status register. two flags per channel in this word (one latched, one unlatched) indicate which function caused the alar m and if the alarm is still present. 77 4 tmpalm the function of this pin is to flag a tempera ture alarm. it is a latched active low open drain output indicating the junction temperature has exceeded either the programmed or default (130degc) temperature setting. two flags in the alarm status register (one latched, one unlatched) indicate if the temperature has dropped below 130deg c or still above. user action is required to clear this latched alarm flag, by writing to the cl ear bit in any of the pmu registers. 78 3 reset active low, level sensitive input used to re set all internal nodes on the device to their power-on reset value. 3, 18, 43, 58 78, 63, 38, 23 c comp (0-3) compensation capacitor input per channel. see section on compensation capacitors.. 2, 19, 42, 59 79, 62, 39, 22 c ff (0-3) external capacitor optimizing the stability performance of the force amplifier (per channel).. see section on compensation capacitors 80, 21, 40, 61 1, 60, 41, 20 extfoh(0-3) per channel, force output for high current range. use external resistor here for current range up to 64ma. 6, 15, 46, 55 75, 66, 35, 26 foh(0-3) per channel force output for all other ranges. 4, 17, 44, 57 77, 64, 37, 24 extmeasih(0-3) per channel sense input (high sense) for high current range. 5, 16, 45, 56 76, 65, 36, 25 extmeasil(0-3) per channel sense input (low sense) for high current range. 9, 12, 49, 52 72, 69, 32, 29 measvh(0-3) per channel dut voltage sense input (high sense) 73 8 dutgnd dut voltage sense input (low sense). by defaul t, dutgnd is shared between all four pmu channels. if user requires a dutgnd input per channel, the guardin (0-3)/dutgnd(0-3) pin may be configured to be a dutgnd input per each pmu channel. 7, 14 , 47, 54 74, 67, 34, 27 guard (0-3) guard output drive. 8, 13, 48, 53 73, 68, 33, 28 guardin(0-3) /dutgnd(0-3) this pin has dual functionality; it may be either a guard input per channel or dutgnd per channel. its function is determined via the serial interface. the power on default is guardin, where it functions as the input to the guard amplifier. alternatively, it may be configured to be used as a dutgnd input per channel. in this case, the input to the guard amplifie r is internally connected to measvh and the guardin /dutgnd pin is used as a dutgnd input per channel. see section on guard amplifier
preliminary technical data ad5522 rev. prm | page 15 of 48 cpol1/sync av s s cpoh3/cpo3 dgnd cpoh1/sdo sdi extfoh2 sync cpoh0/sdi sclk load cpol3/cpo2 cpoh2/cpo1 cpol2/cpo0 extfoh3 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 av s s cpol0/sclk sdo busy dvcc e x t m e a s i l 1 c c o m p 1 c f f 1 a v d d e x t m e a s i h 1 g u a r d 1 g u a r d i n 1 / d u t g n d 1 a g n d m e a s v h 1 m e a s v h 3 a g n d g u a r d i n 3 / d u t g n d 3 g u a r d 3 f o h 3 e x t m e a s i l 3 e x t m e a s i h 3 c c o m p 3 c f f 3 a v d d f o h 1 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 a v d d g u a r d i n 0 d u t g n d 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 a v d d c f f 2 c c o m p 0 a g n d a g n d e x t m e a s i h 0 m e a s v h 2 g u a r d i n 2 \ d u t g n d 2 g u a r d 2 f o h 0 c c o m p 2 e x t m e a s i h 2 g u a r d 0 e x t m e a s i l 0 c f f 0 e x t m e a s i l 2 m e a s v h 0 f o h 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 measout2 av d d measout1 measout0 avss sys_force agnd sys_sense refgnd spi/lvds cgalm vref tmpalm extfoh0 dutgnd extfoh1 avss measout3 avss reset ad5522 top view exposed pad on top (not to scale) figure 9. pin configuration (exposed pad on top of package)
ad5522 preliminary technical data rev. prm | page 16 of 48 terminology offset error offset error is a measure of the difference between actual and ideal voltage expressed in mv. gain error gain error is the differenc e between full-scale error and zero-scale error. it is expressed in %. gain error = full-scale error ? zero-scale error linearity error relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the full-scale range. it is measured after adjusting for offset error and gain erro r and is expressed in % fsr. cm error common mode error is the error at the output of the amplifier due to the common mode input volt age. it is expressed in % of fsr/v. clamp accuracy clamp accuracy is a measure of where the clamps begin to function fully and limit the clamped voltage or current. leakage current current measured at an output pin, when that function is off or high impedance. pin capacitance capacitance measured at a pin when that function is off or high impedance. slew rate the rate of change of output voltage, expressed in v/s. dac specific terms differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1lsb maximum ensures monotonicity. output voltage settling time the amount of time it takes for the output of a dac to settle to a specified level for a full-scale input change. digital-to-analog glitch energy the amount of energy injected into the analog output at the major code transition. the area of the glitch in is specified in nv-s. it is measured by togglin g the dac register data between 0x1fff and 0x2000. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter is defined as the digital crosstalk and is specified in nv-s. digital feedthrough when the device is not selected , high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough.
preliminary technical data ad5522 rev. prm | page 17 of 48 typical performance characteristics figure 10 fv linearity figure 11mv linearity figure 12mi linearity in 2ma range leakage as function of temp, v = 12v -0.5 0 0.5 1 1.5 2 25 35 45 55 65 75 85 95 temp - degc leakage current - na extfoh cff foh extmea sih extmea sil measvh grd_dutgnd combined leakage figure 13leakage as a function of temperature (v = 12v). leakage as f unction of temp, v = 0v -0.2 0 0.2 0.4 0.6 0.8 1 25 45 65 85 temp - degc leakage current - na extfoh cff foh extmea sih extmea sil measvh grd_dutgnd combined leakage figure 14. leakage as a function of temp, (v = 0v) leakage as function of temp, v = -12v -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 25 45 65 85 temp - degc leakage current - na extfoh cff foh extmea sih extmea sil measvh grd_dutgnd combined leakage figure 15. leakage as a function of temp, (v = -12v)
ad5522 preliminary technical data rev. prm | page 18 of 48 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 -12 - 10 -8 - 6 -4 - 2 0 2 4 6 8 10 12 v na extfoh cff foh extmeasih extmeasil measvh grd_dutgnd c ombin ed l eakage figure 16. leakage as a function of voltage (25degc). figure 17noise spectral density figure 18. acpsrr versus frequency
preliminary technical data ad5522 rev. prm | page 19 of 48 functional description the ad5522 is a highly integrated quad per pin parametric measurement unit (ppmu) for use in semiconductor automatic test equipment. it contains programmable modes to force a pin voltage and measure the corresponding current (fvmi), force current measure voltage (fimv), force current measure current (fimi), force voltage measure voltage (fvmv) and force nothing measure voltage (fnmv) or measure current (fnmi). the ppmu can force or measure a voltage range of 22.5 v. it can force or measure currents ranging up to 64ma per channel using the internal amplifier, while the addition of an external amplifier enables higher current ranges. on chip are all the dac levels required for each pmu channel. force amplifier the force amplifier drives the analog output foh, which drives a programmed current or voltage to the dut (device under test). headroom and footroom requirements for this amplifier is 3v on either end. an additional 1v is dropped across the sense resistor when maximum current is flowing through it. this amplifier is designed to drive dut capacitances up to 10nf, with a compensation value of 100pf. larger dut capacitive load will require larger compensation capacitances. local feedback ensures the amplifiers are stable when disabled. a disabled channel reduces power consumption by 2.5ma/channel. comparators per channel, the dut measured value is monitored by two comparators configured as window comparators. internal dac levels set the cpl and cph (low and high) threshold values. there are no restrictions on the voltage settings of the comparator high and lows. cpl going higher than cph is not a useful operation; however, it will not cause any problems to the device. cpol and cpoh are continuous time comparator outputs. table 7. comparator output function test condition cpol cpoh v dut or i dut > cph 0 v dut or i dut < cph 1 v dut or i dut > cpl 1 v dut or i dut < cpl 0 cph > v dut or i dut > cpl 1 1 when using spi interface, full comparator functionality is available. when using the lvds interface, the comparator function is limited to one output per comparator, due to the large pin count requirement of the lvds interface. in this case, comparator output available cpo (0-3) provides information on whether the measured voltage or current is inside or outside the set cph and cpl window. information of whether the measurement was high or low is available via the serial interfaces (comparator status register). table 8. comparator output function using lvds interface test condition cpo output cpl < v dut and i dut < cph 1 cpl > v dut or i dut > cph 0 clamps current and voltage clamps are included on chip per pmu channel. they protect the dut in the event of an open or a short. internal dac levels set the cll and clh (low and high) levels and the clamps work to limit the force amplifier in the event of a voltage or current at the dut exceeding the set levels. the clamps also function to protect the dut when a transient voltage or current spike occurs when changing to a different operating mode or when programming the device to a different current range. the voltage clamps are active while forcing current and the current clamps are active while forcing voltage. by default, the current clamps are off. simply set them up via the status register through the serial interface. the voltage clamps are always active in fi mode. if a clamp level has been hit, this will be flagged via the cgalm open drain output and the resulting alarm information may be read back via the spi or lvds interface. cll should never be greater than clh.
ad5522 preliminary technical data rev. prm | page 20 of 48 current range selection integrated thin film resistors minimize external components and allow easy selection of current ranges from 5 a (200k), 20a (50k), 200a (5k) and 2ma (500). per channel, one current range up to 64ma may be accommodated by connecting an external sense resistor. for current ranges in excess of 64ma, it is recommended an external amplifier be used. for the suggested current ranges, the maximum voltage drop across the sense resistors is 1v, however, to allow for correction of errors, there is some over range available in the current ranges. the full-scale voltage range that can be loaded to the dac is 11.5v; the forced current may be calculated as follows: gain rsense vfin fi = where: fi = forced current vfin = voltage of the fin dac, see v out for dac levels. rsense = selected sense resistor gain of current measure instrumentation amplifier, it may be set (via the serial interface) to 5 or 10. using the 5k sense resistor and isense gain of 10, the maximum current range possible is 225a. similarly for the other current ranges, there is an over range of 12.5% to allow for correction. also, the forced current range will only be the quoted full scale range with an applied reference of 5v or 2.5v (with isense amp gain = 5). the isense amplifier is biased by the offset dac output voltage, in such as way as to center the measure current output irrespective of the voltage span used. when using the extfohx outputs for current ranges up to 64ma, there is no switch in series with the extfohx line, ensuring minimum capacitance presented at the output of the force amplifier. this is also an important feature if using a pin electronics driver to provide high current ranges. high current ranges with the use of an external high current amplifier, one high current range in excess of 64ma is possible. the high current amplifier simply buffers the force output and provides the drive for the required current. dutgnd measvh dut rsense extmeasih extmeasil foh extfoh c ff fin + - internal range select (5ua, 20ua, 200ua, 2ma) 10k ? rsense dac high current buffer - - - - - - + + + + + + x5 or x10 x1 agnd measout x1/x0.2 en offset dac bias to center irange figure 19. addition of high current amplifier for wider current range(>64ma) device under test ground (dutgnd) by default, there is one dutgnd input available for all four pmu channels. in some applications of a pmu, it is necessary that each channel operate from its own dutgnd level. therefore the shared pin guardin(0-3) /dutgnd(0-3) may be configured as either the input to the guard amplifier (guardin), or as a dutgnd per channel function. this may be configured through the serial interface on power on as per required operation. the default connection is sw13b (guardin) and sw14b (dutgnd per device). when configured as dutgnd per channel, this multifunction pin is no longer connected to the input of the guard amplifier, instead it is connected to the low end of the instrumentation amplifier (sw14a), and the input of the guard amplifier is now connected internally to measvh (sw13a). dutgnd measvh (0-3) guard (0-3) guardin (0-3)/ dutgnd (0-3) - - - + + + x1 agndx measure voltage in amp dut guard amp sw 14 sw 13 sw 16 b a b a a figure 20. using the dutgnd per channel feature
preliminary technical data ad5522 rev. prm | page 21 of 48 guard amplifer a guard amplifier allows the user to bootstrap the shield of the cable to the voltage applied to the dut, ensuring minimal drops across the cable. this is particularly important for measurements requiring a high degree of accuracy and in leakage current testing. if not required, all four guard amplifiers may be disabled via the serial interface (through the system control register), this decreases the power consumption by 400ua per channel. as described in the dutgnd section, the guardin(0-3) /dutgnd(0-3) is a shared pin. it can function either as a guard amplifier input per channel or as a dutgnd input per channel as required by the end application. refer to figure 20. a guard alarm event occurs when the guard output moves more than 100mv away from the guard input voltage for more than 200s. in the event this happens, this will be flagged via the cgalm open drain output. as the guard and clamp alarm functions share the same alarm output cgalm , the alarm information (alarm trigger and alarm channel) is available via the serial interface (alarm status register). alternatively, the serial interfaces allow the user to setup the cgalm output to flag either the clamp status or the guard status. by default, this open drain alarm pin is an unlatched output, but may be set to a latched output via the serial interface, system control register. compensation capacitors each channel requires an external compensation capacitor (c comp ) to ensure stability into the maximum load capacitance while ensuring settling time is optimized. in addition, one c ff pin is provided to further optimize stability and settling time performance when in force voltage mode. when changing from force current to force voltage mode, the switch connecting c ff capacitor is automatically closed. while the force amplifier is designed to drive load capacitances up to 10nf (with ccomp = 100pf), using larger compensation capacitor values, it is possible to drive larger load at the expense of an increase in settling time. if a wide range of load capacitance must be driven, then an external multiplexer connected to the c comp pin will allow optimization of settling time versus stability. the series resistance of a switch placed on c comp , should typically be <50. similarly, connecting the c ff node to a multiplexer externally, would cater for a wide range of cdut in force voltage mode. the series resistance of the multiplexer used should be such that: khz cdut ron 100 2 1 > ? ? ? ? ? ? table 9. suggested compensation capacitor selection c load c comp c ff 1nf 100pf 220pf 10nf 100pf 1nf 100nf c load /100 c load /10
ad5522 preliminary technical data rev. prm | page 22 of 48 system force sense switches each channel has switches to allow connection of the force (fohx) and sense (measvhx) lines to a central pmu for calibration purposes. there is one set of sys_force and sys_sense pins per device. for calibration purposes, it is recommended the sys_force path be connected individually to each pmu channel, foh path. temperature sensor an on board temperature sensor monitors temperatures and in the event of the temperature exceeding a factory defined value, (130c) or a user programmable value, the device will protect itself by shutting down all channels and will flag an alarm through the latched open drain tmpalm pin. alarm status may be readback from the alarm status register or the pmu registers where latched and unlatched bits tell if an alarm has occurred and whether the temperature has dropped below the set alarm temperature. measure output (measout) the measured dut voltage or current (voltage representation of dut current) is available on measout (0-3) with respect to agnd. the default measout range is the forced voltage range for voltage measure and current measure (nominally 11.25v, depends on reference voltage and offset dac) and includes some over range to allow for offset correction. the serial interface allows the user to select another measout range of v ref to agnd, allowing for a smaller input range adc to be used. each pmu channel measout line may be made high impedance via the serial interface. when using low supply voltages, ensure that there is sufficient headroom and footroom for the required force voltage range. the offset dac also directly offsets the measure output voltage level, but only when gain1 = 0. table 10. measout output ranges gain1 = 0v ref = 5v gain1 = 1 measout function measout gain = 1 measout gain = 1/5 mv vdut (up to 11.25v) 5 4.5vref to 0 gain0 = 0 current meas gain = 10 v rsense x 10 = up to 11.25v 0 to 4.5v mi gain0 = 1 current meas gain = 5 v rsense x 5 = up to 5.625 0 to 2.25v
preliminary technical data ad5522 rev. prm | page 23 of 48 dac levels each channel contains five dedicated dac levels : one for the force amplifier, one each for the clamp high and low levels and one each for the comparator high and low levels. the architecture of a single dac channel consists of a 16-bit resistor-string dac followed by an output buffer amplifier. this resistor-string architecture guarantees dac monotonicity. the 16-bit binary digital code loaded to the dac register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. the transfer function for dac outputs is: dutgnd code offsetdac v daccode v v ref ref out + ? ? ? ? ? ? ? ? ? ? ? ? ? ? = where the voltage range must be take into account the +/-4v headroom and footroom requirements for the amplifier and sense resistor and must be within the range -16.25v to 22.5v (22v range + 500mv overrange to allow for correction). offset dac the device is capable of forcing a 22.5v (4.5 v ref ) voltage range. included on chip is one 16 bit offset dac (one for all four channels) which allows for adjustment of the voltage range. the useable range is -16.25v to 22.5v. zero scale gives a full- scale range of 0v to +22.5v, mid scale gives 11.25v, while the most negative useful range is in a range of -16.25v to 6.25v. full scale loaded to the offset dac does not give a useful output voltage range as the output amplifiers are limited by available footroom. the following table shows the effect of the offset dac on the other dacs in the device. table 11. offset dac relationship with other dacs with v ref = 5v offset dac code dac code dac output voltage range 0 0 0.00 v 0 32768 11.25 v 0 65535 22.50 v 32768 0 -8.75 v 32768 32768 2.50 v 32768 65535 13.75 v 42130 0 -11.25 v 42130 32768 0.00 v 42130 65535 11.25 v 60855 0 -16.25 60855 32768 -5.00 60855 65535 6.25 65535 - footroom limitations therefore, depending on headroom available, the input to the force amplifier may be unipolar positive, or bipolar, either symmetrical or asymmetrical about dutgnd but always within a voltage span of 22.5v. the offset dac offsets all dac functions. it also centers the current range, such that zero current always flows at midscale code irrespective of offset dac setting. rearranging the transfer function for the dac output gives the following equation to determine what offset dac code is required for a given reference and output voltage range. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? daccode v dutgnd v code offsetdac ref out offset and gain registers each dac level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. these registers give the user the ability to calibrate out errors in the complete signal chain, including the dac, using the internal m and c registers, which hold the correction factors. all registers in the ad5522 are volatile, so need to be loaded on power on during a calibration cycle. the digital input transfer function for each dac can be represented as x2 = [( m + 1)/ 2 n x1 ] + ( c C 2 n C 1 ) where: x2 = the data-word loaded to the resistor string dac. x1 = the 16-bit data-word written to the dac input register. m = code in gain register (default code = 2 16 C 1.) c = code in offset register (default code = 2 15 ) n = dac resolution ( n = 16). the calibration engine is only engaged when data is written to the x1 register. this has the advantage of minimizing the setup time of the device. cached x2 registers each dac has a number of cached x2 values. these registers store the result of an offset and gain calibration in advance of a mode change. this enables the user to preload registers; allow the calibration engine to calculate the appropriate x2 value and store until ready to change modes. as the data is ready and held in the appropriate register, this enables mode changing be as time efficient as possible. if an update occurs to a dac register set that is currently part of the operating pmu mode, the dac output will update immediately (depending on load condition).
ad5522 preliminary technical data rev. prm | page 24 of 48 offset and gain registers for the fin dac the fin (force amplifier input) dac level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. there are six sets of x1, m and c registers, one set (x1, m and c) for the force voltage range, and one set for each of the force current ranges (4 internal current ranges and 1 external current range). six x2 registers store calculated dac values ready to load to the dac register on a mode change. serial i/f fin 16 16 16 x1 reg creg mreg *6 16 16-bit fin dac offset dac x2 reg vref figure 21. fin dac registers offset and gain registers for the comparator dacs the comparator dac levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. there are six sets of (x1, m and c) registers, one set for the voltage mode, and one set for each of the four internal current ranges and one set for the external current range. in this way, x1 may also be preprogrammed, so switching different modes, allows for efficient switching into the required compare mode. six x2 registers store cached calculated dac values ready to load to the dac register on a mode change. vref 16 16 16 cph x1 reg creg mreg 16 16 16 x1 reg creg mreg *6 *6 serial i/f cpl 16 16 16-bit cph dac 16-bit cpl dac x2 reg x2 reg figure 22. comparator registers offset and gain registers for the clamp dacs the clamp dac levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. there are just two sets of registers, one for the voltage mode and another register set (x1, m and c) for all five current ranges. two x2 registers store cached calculated dac values ready to load to the dac register on a pmu mode change. vref x1 reg creg mreg 16 16 16 16 16 16 x1 reg creg mreg serial i/f clh cll 16 16 16-bit clh dac 16-bit cll dac x2 reg x2 reg figure 23. clamp registers v ref one buffered analog input supplies all 20 dacs with the necessary reference voltage to generate the required dc levels. reference selection the voltage applied to the v ref pin determines the output voltage range and span applied to the force amplifier, clamp and comparator inputs. this device can be used with a reference input ranging from 2v to 5v, however, for most applications, a reference input of 5v or 2.5v will be sufficient to meet all voltage range requirements. the dac amplifier gain is 4.5, which gives a dac output span of 22.5v. the dacs have offset and gain registers which can be used to calibrate out system errors. in addition, the gain register can be used to reduce the dac output range to the desired force voltage range. the force dac will retain 16 bit resolution even with a gain register setting of quarter scale (0x4000). therefore, from a single 5v reference, it is possible to get a voltage span as high as 22.5v or as low as 5.625v all from one 5v reference. when using the offset and gain registers, the chosen output range should take into account the system offset and gain errors that need to be trimmed out. therefore, the chosen output range should be larger than the actual, required range. when using low supply voltages, ensure that there is sufficient headroom and footroom for the required force voltage range. also, note that with a supply differential of less than 18v and a full scale current range requirement, it is necessary to reduce the current measure in amp gain to 5 so the feedback path can swing through the full range. also, the forced current range will only be the quoted full scale range with an applied reference of 5v or 2.5v (with isense amp gain = 5). for other voltage/current ranges, the required reference level can be calculated as follows: 1. identify the nominal range required 2. identify the maximum offset span and the maximum gain required on the full output signal range. 3. calculate the new maximum output range including the expected maximum offset and gain errors. 4. choose the new required vout max and vout min , keeping the vout limits centered on the nominal values. note that av dd and av ss must provide sufficient headroom. 5. calculate the value of v ref as follows: v ref = (vout max C vout min )/4.5
preliminary technical data ad5522 rev. prm | page 25 of 48 reference selection example nominal output range = 10v (-2v to +8v) offset error = 100mv gain error = 0.5% refgnd = agnd = 0v 1) gain error = 0.5% => maximum positive gain error = +0.5% => output range incl. gain error = 10 + 0.005(10)=10.05v 2) offset error = 100mv => maximum offset error span = 2(100mv)=0.2v => output range including gain error and offset error = 10.05v + 0.2v = 10.25v 3) v ref calculation actual output range = 10.25v, that is -2.125v to +8.125v (centered); v ref = (8.125v + 2.125v)/4.5 = 2.28v if the solution yields an inconvenient reference level, the user can adopt one of the following approaches: 1. use a resistor divider to divide down a convenient, higher reference level to the required level. 2. select a convenient reference level above v ref and modify the gain and offset registers to digitally downsize the reference. in this way the user can use almost any convenient reference level. 3. use a combination of these two approaches in this case, the optimum reference to choose is a 2.5v reference, then use the m and c registers and the offset dac to achieve the required -2v to +8v range. the isense amplifier gain should be changed to a gain of 5. this ensures a full scale current range of the specified values and also allows optimization of power supplies and minimizes power consumption within the device. calibration the user can perform a system calibration by overwriting the default values in the m and c registers for any individual dac channels as follows: calculate the nominal offset and gain coefficients for the new output range (see previous example) calculate the new m and c values for each channel based on the specified offset and gain errors calibration example nominal offset coefficient = 32768 nominal gain coefficient = 10/10.25x 65535 = 63937 12/12.26 65535 = 64145 example 1: gain error = 0.5% offset error = 100mv 1) gain error (0.5%) calibration: 63937 0.995 = 63617 => load code 0b1111 1000 1000 0001 to m register 2) offset error (100mv) calibration: lsb size = 10.25/65535 = 156 v; offset coefficient for 100mv offset = 100/0.156 = 641 lsbs => load code 0b0111 1101 0111 1111 to c register system level calibration there are many ways to calibrate the device on power on. the following gives an example of how to calibrate the fin dac of the device without a dut or dut board connected. calibration procedure for force and measure circuitry: 1) calibrate force voltage (2 point) write zero scale to the force dac (fin), connect sys_force to fohx and sys_sense to measvhx, close the internal force/sense switch (sw 7). using the system pmu, measure the error between voltage at fohx, measvhx and desired value. similarly, load full scale to the force dac, and measure the error between fohx , measvh and the desired value. work out m and c values. load these values to appropriate m and c registers for force dac. 2) calibrate measure voltage (2 point) connect sys_force to foh, sys_sense to measvhx close internal force/sense switch (sw 7). force voltage on foh via sys_force and measure voltage at measout. the difference is the error between the actual forced voltage and the voltage at measout. 3) calibrate force current (2 point) in force current mode, write zero and fullscale to the force dac. connect sys_force to external ammeter and to foh pin. measure error on zero and fullscale current and calculate m and c values. 4) calibrate measure current (2 point) write zero scale to the force dac in force current mode. connect sys_force to an external ammeter and to the foh pin. measure the error between ammeter reading and measout reading. repeat with full scale loaded to the force dac. 5) repeat for all four channels. similarly, calibrate the comparators and clamp dacs and load the appropriate gain and offset registers. calibrating these dacs will require some successive approximation to find where the comparator trips or the clamps engage.
ad5522 preliminary technical data rev. prm | page 26 of 48 circuit operation force voltage, fv most pmu measurements are performed while in force voltage and measure current mode, for example, when the device is used as a device power supply, or in continuity or leakage testing. in the force voltage mode, the voltage forced is mapped directly to the dut. the voltage measure amplifier completes the loop giving negative feedback to the forcing amplifier. see figure 24. forced voltage at dut = vfin where: vfin = voltage of the fin dac, see v out for dac levels. dutgnd measvh dut rsense up to (64ma) extmeasih extmeasil foh extfoh c ff fin + - internal range select (5ua, 20ua, 200ua, 2ma) rsense dac - - - - - - + + + + + + x5 or x10 x1 agnd measout x1/x0.2 10k ? offset dac bias to center irange figure 24. forcing voltage, measuring current
preliminary technical data ad5522 rev. prm | page 27 of 48 force current, fi in the force current mode, the voltage at fin is now converted to a current and applied to the dut. the feedback path is now the current measure amplifier, feeding back the voltage measured across the sense resistor and measout reflects the voltage measured across the dut. see figure 25. for the suggested current ranges, the maximum voltage drop across the sense resistors is 1v, however, to allow for correction of errors, there is some over range available in the current ranges. the maximum full-scale voltage range that can be loaded to the fin dac is 11.5v; the forced current may be calculated as follows: gain rsense vfin fi = where: fi = forced current vfin = voltage of the fin dac, see v out for dac levels. rsense = selected sense resistor gain of current measure instrumentation amplifier, it may be set (via the serial interface) to 5 or 10. the isense amplifier is biased by the offset dac output voltage, in such as way as to center the measure current output irrespective of the voltage span used. using the 5k sense resistor and isense gain of 10, the maximum current range possible is 225a. similarly for the other current ranges, there is an over range of 12.5% to allow for correction. dutgnd measvh dut rsense up to (64ma) extmeasih extmeasil foh extfoh c ff fin + - measout internal range select (5ua, 20ua, 200ua, 2ma) rsense dac x1/x0.2 - - - - - - + + + + + + x5 or x10 x1 agnd 10k ? figure 25. .forcing current, measuring voltage
ad5522 preliminary technical data rev. prm | page 28 of 48 serial interface the ad5522 contains two high-speed serial interfaces, an spi compatible, interface operating at clock frequencies up to 50mhz, and an eia-644-compliant, lvds interface. to minimize both the power consumption of the device and on- chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . spi interface the serial interface operates over a 2.3v to 5.25v dv cc supply range. the serial interface is controlled by four pin, as follows: sync frame synchronization input. sdi serial data input pin. sclk clocks data in and out of the device. sdo serial data output pin for data readback purposes. there is also an spi /lvds select pin, which must be held low for spi interface and high for lvds interface. lvds interface the lvds interface uses the same input pins as the spi interface with the same designations. in addition, three other pins are provided for the complementary signals needed for differential operation, thus: sync/ sync differential frame synchronization signal. sdi/ sdi differential serial data input. sclk/ sclk differential clock input. sdo/ sdo serial data output pin for data readback serial interface write mode the ad5522 allows writing of data via the serial interface to every register directly accessible to the serial interface, which is all registers except the dac registers. the serial word is 29 bits long. the serial interface works with both a continuous and a burst (gated) serial clock. serial data applied to sdi is clocked into the ad5522 by clock pulses applied to sclk. the first falling edge of sync starts the write cycle. at least 29 falling clock edges must be applied to sclk to clock in 29 bits of data, before sync is taken high again. the input register addressed is updated on the rising edge of sync . in order for another serial transfer to take place, sync must be taken low again. reset function bringing the level sensitive reset line low resets the contents of all internal registers to their power-on reset state (detailed in the section power on default). this sequence takes approx 300s. the falling edge of reset initiates the reset process; busy goes low for the duration, returning high when reset is complete. while busy is low, all interfaces are disabled. when busy returns high, normal operation resumes and the status of the reset pin is ignored until it goes low again. the sdo output will be high impedance during a power on reset or a reset . power on reset follows the same function as reset . busy and load function busy is an open drain output that indicates the status of the ad5522 interface. when writing to any of the registers busy goes low and stays low until the command completes. writing to a dac register drives the busy signal low for longer than a simple pmu or system control register write. for the dacs, the value of the internal cached (x2) data is calculated and stored each time the user writes new data to the corresponding x1 register. during this write and calculation, the busy output is driven low. while busy is low, the user can continue writing new data to the x1, m, or c registers, but no output updates can take place. x2 values are stored and held until a pmu word is written that calls the appropriate cached x2 register. only then does a dac output update. the dac outputs and pmu modes are updated by taking the load input low. if load goes low while busy is active, the load event is stored and the dac outputs or pmu modes update immediately after busy goes high. a user can also hold the load input permanently low. in this case, the change in dac outputs or pmu modes update immediately after busy goes high. the busy pin is bidirectional and has a 50 k? internal pullup resistor. where multiple ad5522 devices may be used in one system, the busy pins can be tied together. this is useful where it is required that no dac or pmu in any device is updated until all others are ready. wh en each device has finished updating the x2 registers, it will release the busy pin. if another device has not finished updating its x2 registers, it will hold busy low, thus delaying the effect of load going low. as there is only one multiplier shared between four channels, this task must be done sequentially, so the length of the busy pulse will vary according to th e number of channels being updated.
preliminary technical data ad5522 rev. prm | page 29 of 48 table 12. busy pulse width action busy pulse width ( s max) loading data to pmu, system control register or readback 0.27 loading x1 to any 1 pmu dac channel 1.25 loading x1 to any 2 pmu dac channels 1.75 loading x1 to any 3 pmu dac channels 2.25 loading x1 to any 4 pmu dac channels 2.75 busy pulse width = ((number of channels +1) 500ns) + 250ns busy also goes low during power-on reset and when a falling edge is detected on the reset pin. write #1 1st stage 2nd stage 3rd stage ~600ns 500ns 500ns 250ns calibration engine time e.g. write to 3 fin dac registers 1st stage 2nd stage 3rd stage 1st stage 2nd stage 3rd stage 1st stage 2nd stage 3rd stage write #2 figure 26. multiple writes to dac x1 registers writing data to the system control register, pmu control register, m or c registers do not involve the digital calibration engine, thus speeding up configuration of the device on power on. register update rates as mentioned previously the value of the x2 register is calculated each time the user writes new data to the corresponding x1 register. the calculation is performed by a three stage process. the first two stages take 500ns each and the third stage takes 250ns. when the writes to one of the x1 registers is complete the calculation process begins. if the write operation involves the update of a single dac channel the user is free to write to another register provided that the write operation doesnt finish until the first stage calculation is complete, i.e. 500ns after the completion of the first write operation. ~600ns 500ns 500ns 250ns calibration engine time 1st stage 2nd stage 3rd stage write #1 1st stage 2nd stage 3rd stage write #2 1st stage 2nd stage 3rd stage write #3 figure 27. multiple single channel writes engaging calibration engine
ad5522 preliminary technical data rev. prm | page 30 of 48 register selection the serial word assignment consists of 29 bits. bits 28 through to 22 are common to all registers, whether writing to or reading from the device. pmu3 to pmu0 data bits address each pmu channel (or associated dac register). when pmu3 to pmu0 are all zeros, the system control register is addressed. mode bits mode0 and mode1 address the different sets of dac registers and the pmu register. readback control, rd/ wr the r/ w bit set high initiates a readback sequence of pmu, alarm, comparator, system control register or dac information as determined by address bits. pmu address bits, pmu3, pmu2, pmu1, pmu0 bits pmu3 through pmu0 address each of the pmu channels on chip. this allows individual control of each pmu channel or any manner of combined addressing in addition to multi channel programming. pmu bits also allow access to write registers such as the system control register and the many dac registers, in addition to reading from all the registers. table 13. mode bits b23 b22 write function mode1 mode0 action 0 0 system control register or pmu register 0 1 dac gain (m) register 1 0 dac offset (c) register 1 1 dac input data register, (x1) table 14. read and write functions of the ad5522 b28 b27 b26 b25 b24 b23 b22 b21 to b0 selected register rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 data bi ts ch3 ch2 ch1 ch0 write functions 0 0 0 0 0 0 0 data bits write to system control register ( table 16 ) 0 0 0 0 0 0 1 data bits reserved 0 0 0 0 0 1 0 data bits reserved 0 0 0 0 0 1 1 11 1111 1111 1111 1111 1111b nop (no operation) 0 0 0 0 0 1 1 data bits other than all 1s reserved write addressed dac or pmu register 0 0 0 0 1 cho 0 0 0 1 0 ch1 0 0 0 1 1 ch1 ch0 0 0 1 0 0 ch2 0 - - - - - - - - 0 1 0 0 0 ch3 0 - - - - - - - - 0 1 1 1 0 ch3 ch2 ch1 0 1 1 1 1 select dac or pmu registers. see table 13 data bits ch3 ch2 ch1 ch0 read functions 1 0 0 0 0 0 0 all zeros read fr om system control register 1 0 0 0 0 0 1 all zeros read from comparator status registers 1 0 0 0 0 1 0 x reserved 1 0 0 0 0 1 1 all zeros read from alarm status register read addressed dac or pmu register C can only read one pmu or dac register at one time. 1 0 0 0 1 ch0 1 0 0 1 0 ch1 1 0 1 0 0 ch2 1 1 0 0 0 pmu/dac register address see table 13 dac address see table 21 ch3 nop (no operation) if a nop (no operation) command is loaded, no change is made to dac or pmu registers. this code is useful when performing a rea d back of a register within the device (via the sdo pin) wher e a change of dac code or pmu function may not be required reserved commands any bit combination that is not described in the register address tables for the pmu, dac and system control registers are rese rved commands. these commands are unassigned commands; they are reserved for factory use. to ensure correct operation of the device, do not used reserved commands.
preliminary technical data ad5522 rev. prm | page 31 of 48 write system control register the system control register is accessed when the pmu cha nnel address pmu3-pmu0 and mode bits, mode1 and mode0 are all zeros. it allows quick setup of different functions within the device. the system control register operates on a per device bas is. table 15. system control register bits b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b1 4 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1/0 rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 cl3 cl2 cl1 cl0 cpolh3 cpolh2 cpolh1 cpolh0 cpbiasen dutgnd/ch guard alm clamp alm int10k guard en gain1 gain0 tmp enable tmp1 tmp0 latched 0 table 16. system control register functions bit bit name description 28 (msb) rd/ wr when low, a write function takes place to the selected register, while if the rd/ wr bit is set high, this initiates a readback sequence of pmu, alarm, comparator, system control or dac register as determined by address bits. 27 pmu3 26 pmu2 25 pmu1 24 pmu0 bits pmu3 through pmu0 address each of the pmu channels in the device. if all four of these bits are set to zero, the system co ntrol register is addressed. b27 b26 b25 b24 b23 b 22 selected register pmu3 pmu2 pmu1 pmu0 mode1 mode0 ch3 ch2 ch1 ch0 0 0 0 0 0 0 write to system control register 0 0 0 1 cho 0 0 1 0 ch1 0 0 1 1 ch1 ch0 0 1 0 0 ch2 - - - - - - - - 1 0 0 0 ch3 - - - - - - - - 1 1 1 0 ch3 ch2 ch1 1 1 1 1 select dac or pmu registers. see below ch3 ch2 ch1 ch0 23 mode1 22 mode0 mode bits, mode0 and mode1 allow ad dressing of the pmu register or the dac gain (m), offset (c ) or input register (x1). set t o zero to access the system control register. mode1 mode0 action 0 0 system control register or pmu register 0 1 dac gain (m) register 1 0 dac offset (c) register 1 1 dac input data register, (x1) system control register specific bits 21 cl3 20 cl2 19 cl1 18 cl0 current clamp enable. bits cl3 through cl0 enable and disable th e current clamp function per channel. a 0 disables, while a 1 enables. the clamp enable function is also available in the pmu register on a per ch annel basis. this dual functionality allows flexible enable or disabling of this functi on. when reading back information on the status of the clamp enable function, what w as most recently written to the current clamp register is available in the readback word from either pmu or system control registe rs. the voltage clamps (fi mode) are always enabled. 17 cpolh3 16 cpolh2 15 cpolh1 14 cpolh0 comparator output enable. by default the comparator outputs are hi-z on power on. a 1 in each bit position enables the comparator output for the selected channel. the cpbiasen (bit 13) must be enabled to power on the comparator functions. the comparator enable function is also available in the pmu register on a per channel basis. this du al functionality allows flexibl e enable or disabling of this function. when reading back informat ion on the status of the comparator enable function, what was most recently written to the comparator register is available in the readback word from either pmu or system control registers. 13 cpbiasen comparator enable. by default the comparators are powered down on powe r on. to enable the comparator function for a ll channels, write a 1 to the cpbiasen bit. a 0 disabled the co mparators and shuts them down. comparator output enables bits (cpolhx) allow the user to switch on each comparator outp ut individually, enabling bussing of comparator outputs. 12 dutgnd/ch dutgnd per channel enable. the guardin(0-3) /dutgnd(0-3) pins are shared pin functions and may be configured to enable a dutgnd per pmu channel or guard input per pmu channel. setting th is bit to 1 enables dutgnd per channel. in this mode, this pin now functions as a dutgnd pin on a per channel basis. the gu ard inputs are disconnected from this pin and instead connected directly to the measvh line by an internal connection. default po wer on condition is guardin(0-3). 11 guard alm 10 clamp alm clamp and guard alarm function share one open drain cgalm alarm pin. by default, the cgalm pin is disabled. bits guard alm and clamp alm allow the user to choose if they only wish to have both or either information flagged to the cgalm pin. set high to enable either alarm function. 9 int10k internal sense short, int10k. setting this bit high allows the user to connec t in an internal sense short resistor of 10k? between the foh and the measvh lines, (closes sw 7), it also closes sw 15, connecting another 10 k? resistor between dutgnd and agnd.
ad5522 preliminary technical data rev. prm | page 32 of 48 8 guard en guard enable. the guard amplifier is disabled on po wer on; write a 1 to enable it. disabling the guard function i f not in use saves power (typically 400a per channel). 7 gain1 6 gain0 measout output range. the measout range de faults to the voltage force span for vo ltage and current measurements, this is 11.25v, which includes some over range to allow for offset correction. the measout range may be reduced by using the gain0 and gain1 data bits. this allows for use of asymmetrical supplies and also for use of a smaller input range adc. gain1 = 0v ref = 5v gain1 = 1 measout function measout gain = 1 measout gain = 1/5 mv vdut (up to 11.25v) 5 4.5vref to 0 gain0 = 0 current meas gain = 10 v rsense x 10 = up to 11.25v 0 to 4.5v mi gain0 = 1 current meas gain = 5 v rsense x 5 = up to 5.625 0 to 2.25v 5 tmp enable 4 tmp1 3 tmp0 thermal shutdown function, tmp enable, tmp1, tmp0 to disable the thermal shutdown feature, write a 0 to the tmp enable bit (enabled by default). bits tmp1 and tmp0 allow the user to program the thermal shutdown temperature of operation. tmp enable tmp1 tmp0 action 0 x x thermal shutdown disabled 1 x x thermal shutdown enabled 1 0 0 shutdown at junction temp of 130c (power on default) 1 0 1 shutdown at junction temp of 120c 1 1 0 shutdown at junction temp of 110c 1 1 1 shutdown at junction temp of 100c 2 latched configure open drain cgalm as a latched or unlatched output pin. when high, this bit sets the cgalm alarm output as latched outputs allowing it to drive a controller i/o without having to poll the line constantly. default condition on power on is unla tched. 1 0 0 (lsb) 0 unused bits. set to 0.
preliminary technical data ad5522 rev. prm | page 33 of 48 write pmu register to address pmu functions, set mode bits mode1, mode0 low, this selects the pmu register as outlined in table 13 and table 14. t he ad5522 has very flexible addressing, in that it allows writing of data to a single pmu channel, any combination of them or all pmu channels. this enables multi pin broadcasting to similar pins on a dut. bits 27 to 24 select which pmu or group of pmus is addr essed. table 17. pmu register bits b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 to b 0 rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 ch en force1 force0 x c2 c1 c0 meas1 meas0 fin sf0 sf0 cl cpolh compare v/i clear unused data bits table 18. pmu register functions bit bit name description 28 (msb) rd/ wr when low, a write function takes place to the selected register, while if the rd/ wr bit is set high, this initiates a readback sequence of pmu, alarm, comparat or, system control or dac register as determined by address bits. 27 pmu3 26 pmu2 25 pmu1 24 pmu0 bits pmu3 through pmu0 address each of the pmu channels in th e device. this allows individual control of each pmu channel or any manner of combined addressing in addition to multi-channel programming. b27 b26 b25 b24 b23 b 22 selected register pmu3 pmu2 pmu1 pmu0 mode1 mode0 ch3 ch2 ch1 ch0 0 0 0 0 0 0 write to system control register 0 0 0 1 cho 0 0 1 0 ch1 0 0 1 1 ch1 ch0 0 1 0 0 ch2 - - - - - - - - 1 0 0 0 ch3 - - - - - - - - 1 1 1 0 ch3 ch2 ch1 1 1 1 1 select dac or pmu registers. see below ch3 ch2 ch1 ch0 23 mode1 22 mode0 mode bits, mode0 and mode1 allow addressing of the pmu register or the dac gain (m), offset (c ) or input register (x1). set to zero to access the pmu register. mode1 mode0 action 0 0 system control register or pmu register 0 1 dac gain (m) register 1 0 dac offset (c) register 1 1 dac input data register, (x1) pmu register specific bits 21 ch en channel enable, set high to enable the selected channel, similarly, set low to disable a selected channel or group of channels. when disabled, sw 2 is closed, sw 5 open. 20 force1 19 force0 bits force1 and force0 address the force function for ea ch of the pmu channels (in association with p3-p0). all combinations of forcing and measuring (usi ng meas0 and meas1) are available. the hi -z (voltage and current) modes allows user to optimize glitch response during mode changes. while in these modes, with pmu hi-z, new x1 codes loaded to the fin dac register and the clamp dac register will be calibrated, stor ed in x2 register and loaded directly to the dac outputs. force1 force0 action 0 0 fv & current clamp (if clamp enabled) 0 1 fi & voltage clamp (if clamp enabled) 1 0 hi-z foh voltage (pre load fin dac & clamp dac) 1 1 hi-z foh current (pre load fin dac & clamp dac) 18 reserved 0 17 c2 16 c1 15 c0 bits c2 through c0 address allow selection of the required current range. c2 c1 c0 action 0 0 0 5a current range 0 0 1 20a current range 0 1 0 200a current range 0 1 1 2ma current range 1 0 0 external current range 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
ad5522 preliminary technical data rev. prm | page 34 of 48 14 meas1 13 meas0 bits meas1 and meas0 allow selection of the required measure mode, allowing the measout line to be disabled, connected to the temperature sensor or enabled for measurement or current or voltage. meas1 meas0 action 0 0 measout connected to i sense 0 1 measout connected to v sense 1 0 measout connected to temperature sensor 1 1 measout hi-z (sw 12 open) 12 fin bit fin = 0 switches the input of the force amplifie r to gnd, while fin = 1 connects it to fin dac output. 11 sfo 10 sso bits sf0 through ss0 address each of the different combinations of switching the system force and sense lines to the force and sense at the dut. selection of which channel the system force and sense lines are connected to as per p3 to p0 addressing. for correct operation, only one pmu channel should be connected at any one time to the sys_force/sys_sense paths. sf0 ss0 action 0 0 sys_force and sys_sense hi-z 0 1 sys_force hi-z, sys_sense connected to measvhx 1 0 sys_force connected to fohx, sys_sense hi-z 1 1 sys_force connected to fohx, sys_sense connected to measvhx 9 cl per pmu current clamp enable bit. a logic high enables the clamp function for the selected pmu. the current clamp enable function is also available in the system control register. this dual functionality allows flexible enable or disabling of this function. when reading back information on the status of the clamp enable function on a per channel basis, what was most recently written to the current clamp register is available in th e readback word from either pmu or system control registers. the voltage clamps (fi mode) are always enabled. 8 cpolh comparator output enable bit. a lo gic high enables the comparator output for the selected pmu, the comparator function cpbiasen must be enabled in the system control register. th e comparator output enable fu nction is also available in the system control register. this dual functionality allo ws flexible enable or disa bling of this function. 7 compare v/i a logic high selects compare voltag e function, while logic low, current function. 6 clear to clear or reset a latched alarm bit and pin (temperatu re, guard or clamp), load a 1 to the clear bit position. this bit applies to latched alarm (clamp and guard) co nditions on all four pmu channels. 5 4 3 2 1 0 (lsb) 0 unused bits. set to 0.
preliminary technical data ad5522 rev. prm | page 35 of 48 write dac register the dac input, gain and offset registers are addressed through a combination of pmu bits (bits 27 through 24) and mode bits (bi ts 23 and 22). bits a5 through a0 address each of the dac levels on chip. d15 through d0 are the dac data bits when writing to these registers. pmu address bits allow addressing to dac across any combination of pmu channels. table 19. dac register bits b28 b27 b26 b25 b24 b 23 b22 b21 b20 b19 b 18 b17 b16 b15 to b0 rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 a5 a4 a3 a2 a1 a0 data bits d15 (msb to d0 (lsb) table 20. dac register functions bit bit name description 28 (msb) rd/ wr when low, a write function takes place to the selected register, while if the rd/ wr bit is set high, this initiates a readback sequence of pmu, alarm, comparator, system co ntrol or dac register as determined by address bits. 27 pmu3 26 pmu2 25 pmu1 24 pmu0 bits pmu3 through pmu0 address each of the pmu and dac channels in the device. this allows individual control of each dac channel or any manner of combined addressing in addition to multi-channel programming. b27 b26 b25 b24 b23 b 22 selected register pmu3 pmu2 pmu1 pmu0 mode1 mode0 ch3 ch2 ch1 ch0 0 0 0 0 0 0 write to system control register 0 0 0 1 cho 0 0 1 0 ch1 0 0 1 1 ch1 ch0 0 1 0 0 ch2 - - - - - - - - 1 0 0 0 ch3 - - - - - - - - 1 1 1 0 ch3 ch2 ch1 1 1 1 1 select dac or pmu registers. see below ch3 ch2 ch1 ch0 23 mode1 22 mode0 mode bits, mode0 and mode1 allow addressing of the da c gain (m), offset (c ) or input register (x1) mode1 mode0 action 0 0 system control register or pmu register 0 1 dac gain (m) register 1 0 dac offset (c) register 1 1 dac input data register, (x1) dac register specific bits 21,20,19 a5,a4,a3 dac address bits. a5 to a3 sele ct which register set is addressed. see table 21 18,17,16 a2,a1,a0 dac address bits, a2 to a0 select which dac is addressed. see table 21 15 to 0(lsb) d15 (msb) to d0(lsb) 16 dac data bits. d15 msb.
ad5522 preliminary technical data rev. prm | page 36 of 48 dac addressing for the fin and comparator (cph & cpl) dacs, there are sets of x1, m and c registers for each current range and for the voltage range, but only two sets for the clamp function (cll and clh). when calibrating the device, m and c registers allow volatile storage of offset and gain coefficients. calculation of the corre sponding dac x2 register only occurs when x1 data is loaded (no internal calculation occurs on m or c updates). there is one offset dac per all four channels in the device, it is addressed through any pmu0-3 address. the offset dac only ha s an input register associated with it; there are no m or c registers for this dac. when writing to this dac, set both mode bits hig h to address the dac input register (x1). this address table is also used for readback of a particular dac address. table 21. dac register addressing address bits a5 to a3 (dac address register) register set 000 001 010 011 100 101 110 111 mode1 mode0 0 1 reserved 1 0 reserved 000 5a i range 1 1 offset dac fin reserved reserved cpl cph reserved reserved 001 20a i range reserved fin reserved reserved cpl cph reserved reserved 010 200a i range reserved fin reserved reserved cpl cph reserved reserved 011 2ma i range reserved fin reserved reserved cpl cph reserved reserved 100 external i range reserved fin cll i 1 clh i 1 cpl cph reserved reserved 101 voltage range reserved fin cll v 2 clh v 2 cpl cph reserved reserved 110 reserved reserved reserved reserved reserved reserved reserved reserved reserved a2 to a0 (register address) 111 reserved reserved reserved reserved reserved reserved reserved reserved reserved 1 cll i = clamp level low current register. clh i = clamp level hi gh current register. when forcing a voltage, current clamps ar e engaged, so this register set will be loaded to the clamp dac. 2 cll v = clamp level low voltage register. clh v = clamp level high voltage register . when forcing a current, voltage clamps ar e engaged, so this register set will be loaded to the clamp dac.
preliminary technical data ad5522 rev. prm | page 37 of 48 read registers readback of all the registers in the device is possible via the both spi and lvds interfaces. in order to readback data from a register, it is first necessary to write a readback command to tell the device which register is required to readback. see table 22 to addres s the appropriate channel. table 22. read functions of the ad5522 b28 b27 b26 b25 b24 b23 b22 b21 to b0 selected register rd/ wr pmu3 pmu2 pmu1 pmu0 mode1 mode0 data bits ch3 ch2 ch1 ch0 read functions 1 0 0 0 0 0 0 all zeros read from system control register 1 0 0 0 0 0 1 all zeros read from comparator status registers 1 0 0 0 0 1 0 x reserved 1 0 0 0 0 1 1 all zeros read from alarm status register read addressed pmu register C only one pmu register can be read at one time 1 0 0 0 1 0 0 ch0 1 0 0 1 0 0 0 ch1 1 0 1 0 0 0 0 ch2 1 1 0 0 0 0 0 all zeros ch3 read addressed dac m register C only one dac register can be read at one time 1 0 0 0 1 0 1 ch0 1 0 0 1 0 0 1 ch1 1 0 1 0 0 0 1 ch2 1 1 0 0 0 0 1 dac address see table 21 ch3 read addressed dac c register C only one dac register can be read at one time 1 0 0 0 1 1 0 ch0 1 0 0 1 0 1 0 ch1 1 0 1 0 0 1 0 ch2 1 1 0 0 0 1 0 dac address see table 21 ch3 read addressed dac x1 register C only one dac register can be read at one time 1 0 0 0 1 1 1 ch0 1 0 0 1 0 1 1 ch1 1 0 1 0 0 1 1 ch2 1 1 0 0 0 1 1 dac address see table 21 ch3 once the required channel has been addressed, the device will load the 24 bit readback data into the msb positions of the 29 bi t serial shift register, the five lsb bits will be filled with zeros. sclk rising edges clock this readback data out on sdo(framed by th e sync signal). a minimum of 24 clock rising edges are required to shift the readback data out of the shift register. if writing a 24-bit word to shift data out of the device, user must ensure that the 24 bit write is effectively a nop (no operation) command. the last 5 bits in the s hift register will always be 00000b, these five bits will become the msbs of the shift register when the 24 bit write is loaded. to ensure th e device receives a nop command as outlined in table 14, the recommended flush command is 0xffffff and no change will be made to any register within the device. readback data may also be shifted out by writing another 29 bit write or read command. if writing a 29-bit command, the readbac k data will be msb data available on sdo, followed by 00000b.
ad5522 preliminary technical data rev. prm | page 38 of 48 readback of system control register the readback function is a 24 bit word, mode, address and system control register data bits as shown in the following table. table 23. readback system control register data bit bit name description 23 (msb) mode1 0 22 mode0 0 system control register specific readback bits 21 cl3 20 cl2 19 cl1 18 cl0 readback the status of the individual clamp enable bits . a 0 means the clamp is disabled, while a 1 enabled. the clamp enable function is also available in the system control register. this dual functionality allows flexible enable or disabling of this function. when reading back information on the status of the clamp enable function, what was most recently written to the clamp register from either system control register or pmu register will be available in the readback word. 17 cpolh3 16 cpolh2 15 cpolh1 14 cpolh0 readback information on the comparator output enable st atus. a 1 signifies the function is enabled, while a 0 disabled. a logic high indicates that the pmu comparator output is enabled, while if low, its disabled. the comparator output enable function is also available in the pmu register. this dual functionality allows flexible enable or disabling of this function. when reading back information on the status of the comparator output enable function, what was most recently written to the co mparator register from either system control register or pmu register will be available in the readback word. 13 cpbiasen this readback bit tells the st atus of the comparator enable function . a 1 in this bit position means the comparator functions are enabled, while a 0 disabled. 12 dutgnd/ch dutgnd per channel enable. if th is bit is set at 1, dutgnd per channe l is enabled, while if 0, individual guard inputs are available per channel. 11 guard alm 10 clamp alm these bits give status on which of these alarm bits trigger the cgalm pin. 9 int10k if this bit is set high, the internal 10k resist or is connected between foh and measvh, and between dutgnd and agnd. if low, they are disconnected. 8 guard en readback status of the guard ampl ifies. if high, amplifiers are enabled. 7 gain1 6 gain0 status of the selected measout output range. 5 tmp enable 4 tmp1 3 tmp0 information is available on the status of the setting for thermal shutdown function. refer to system control write register. 2 latched this bit tells of the status of the open drain ou tputs. when high, the open drain alarm outputs are latched outputs, while if low, they are unlatched. 1 0 (lsb) unused readback bits will be loaded with zeros.
preliminary technical data ad5522 rev. prm | page 39 of 48 readback of pmu register the pmu readback function is a 24 bit word, mode, address and pmu data bits. table 24. readback pmu register (only one pmu register may be read back at any one time). bit bit name description 23 (msb) mode1 0 22 mode0 0 pmu register specific bits 21 ch en channel enable, if high selected channel is enabled, otherwise disabled. 20 force1 19 force0 these bits tell what force and measure mode the selected channel is in. 18 reserved 0 17 c2 16 c1 15 c0 these three bits tell what forced or measured current range is set for the selected channel. 14 meas1 13 meas0 bits meas1 and meas0 tell which measure mode is sele cted, voltage, current, temperature sensor or hi- z. 12 fin this bit shows the status of the force input amplifier. 11 sfo 10 sso the system force and sense lines may be connected to any of the four pmu channels. reading back these bits tell if they are switched in or not. 9 cl a logic high in this readback position tells if th e per pmu clamp is enabled, while if low, the clamp is disabled. the clamp enable function is also avai lable in the system control register. this dual functionality allows flexible enable or disabling of this function. when reading back information on the status of the clamp enable function, what was most recently written to the clamp register from either system control register or pmu register wi ll be available in the readback word. 8 cpolh a logic high indicates that the pmu comparator output is enabled, while if low, its disabled. the comparator output enable function is also avai lable in the system control register. this dual functionality allows flexible enable or disabling of this function. when reading back information on the status of the comparator output enable function, what was most recently written to the comparator register from either system control register or pm u register will be available in the readback word. 7 compare v/i a logic high selects indicates the selected cha nnel is comparing voltage function, while logic low, current function. 6 ltmpalm 5 tmpalm tmpalm corresponds to the open drain tmpalm output pin which flags the user of a temperature event exceeding the default or user programmed level. the temperature alarm is a per device alarm, and latched ( ltmpalm ) and unlatched ( tmpalm ) bits tell a temperature event occurre d and if the alarm still exists (if the junction temperature still exceeds the programmed alarm level). to reset an alarm event, the user must write to the clear bit in the pmu register. 4, 3, 2, 1, 0 (lsb) unused readback bits will be loaded with zeros. readback of comparator status register the comparator output status register is a read only register giving access to the output status of each of the comparators on the chip. table 25 shows the format of the comparator readback word. table 25. comparator status readback register bit bit name description 23 (msb) mode1 0 22 mode0 1 comparator status register specific bits 21 cp0l0 20 cp0h0 19 cp0l1 18 cp0h1 17 cp0l2 16 cp0h2 15 cp0l3 14 cp0h3 comparator output conditions per channel corresponding to the comparator output pins. 13 to 0 (lsb) unused readback bits will be loaded with zeros.
ad5522 preliminary technical data rev. prm | page 40 of 48 readback of alarm status register the alarm status register is a read only register that gives information on temperature, clamp and guard alarm events. in the e vent the guard and clamp alarm functions are not used, (the alarm function may be switched off in the system control register). in this case, the temperature alarm status is also available in the contents of any of the four pmu readback registers. table 26. alarm status readback register bit bit name description 23 (msb) mode1 1 22 mode0 1 alarm status readback register specific bits 21 ltmpalm 20 tmpalm tmpalm corresponds to the open drain tmpalm output pin which flags the user of a temperature event exceeding the default or user programmed level. the temperature alarm is a per device alarm, and latched ( ltmpalm ) and unlatched ( tmpalm ) bits tell a temperature event occurre d and if the alarm still exists (if the junction temperature still exceeds the programmed alarm level). to reset an alarm event, the user must write to the clear bit in the pmu register. 19 lg0 18 g0 17 lg1 16 g1 15 lg2 14 g2 13 lg3 12 g3 lgx is the per channel latched guard alarm bit and gx is an unlatched alarm bit. these bits give information on which channel flagged an alarm on the open drain alarm cgalm pin and if the alarm condition still exists. 11 lc0 10 c0 9 lc1 8 c1 7 lc2 6 c2 5 lc3 4 c3 lcx is a per channel latched clamp alarm bit and cx is the unlatched alarm bit. these bits give information on which channel flagged an alarm on the open drain alarm cgalm pin and if the alarm condition still exists. 3 to 0 (lsb) unused readback bits will be loaded with zeros. readback of dac register the dac readback function is a 24 bit word, mode, address and dac data bits. table 27. dac register readback bit bit name description 23 (msb) mode1 0 22 mode0 0 dac readback register specific bits 21 to 16 a5, a4, a3, a2, a1 address bits in dicating the dac register that is read. 15 to 0 (lsb) d15 to d0 contents of th e addressed dac register (x1, m or c).
preliminary technical data ad5522 rev. prm | page 41 of 48 power on default the power on default for all dac channels is that the contents of each m register is set to full-scale (0xffff) and c register to midscale(0x8000). the contents of the dac registers are : offset dac: 0xa492, fin dacs: 0x8000, cll dacs: 0x0000, clh dacs: 0xffff, cpl dacs: 0x0000, cph dacs: 0xffff the power on default for the alarm status register is 0xfffff0, while the comparator status registers powers up at 0x400000. th e power on defaults of the pmu register and the system control register are shown below. table 28. power on default for system control register and pmu register system control register power on de fault pmu register power on default bit bit name description bit name description 21 (msb) cl3 0 ch en 0 20 cl2 0 force1 0 19 cl1 0 force0 0 18 cl0 0 reserved 0 17 cpolh3 0 c2 0 16 cpolh2 0 c1 1 15 cpolh1 0 c0 1 14 cpolh0 0 meas1 1 13 cpbiasen 0 meas0 1 12 dutgnd/ch 0 fin 0 11 guard alm 0 sfo 0 10 clamp alm 0 sso 0 9 int10k 0 cl 0 8 guard en 0 cpolh 0 7 gain1 0 compare v/i 0 6 gain0 0 ltmpalm 1 5 tmp enable 1 tmpalm 1 4 tmp1 0 0 3 tmp0 0 0 2 latched 0 0 1 0 0 0 (lsb) unused data bits 0 unused data bits 0
ad5522 preliminary technical data rev. prm | page 42 of 48 setting up the device on power on on power on, default conditions are recalled from the power on reset register ensuring each pmu and dac channel is powered up to a known condition. to operate the device, the user must: 1) configure the device by writing to the system control register to set up different functions as required. 2) calibrate out errors and load required calibration values to (gain) m and (offset) c registers, and load codes to each dac input register (x1). once x1 values are loaded to the individual dacs, the calibration engine calculates the appropriate x2 value and stores it ready for the pmu address to call it. 3) load the required pmu channel with the required force mode, current range etc. loading the pmu channel configures the switches around the force amplifier, measure function, clamps and comparators and also acts as a load signal for the dacs, loading the dac register with the appropriate stored x2 value. 4) as the voltage and current ranges have individual dac registers associated with them, each pmu register mode of operation calls a particular x2 register. hence, only updates (changes to x1 register) to dacs associated with the selected mode of operation are reflected to the output of the pmu. if there is a change to the x1 value associated with a different pmu mode of operation, then this x1 value and its m and c coefficients are used to calculate a corresponding x2 value which is stored in the correct x2 register, but it does not get loaded to the dac. changing modes there are different ways of handling a mode change: 1) load any dac x1 values that are required to change. remember that x1 registers are available per voltage and current range (for force amplifier and comparator dacs), so you can preload these and may not need to make changes. the calibration engine will calculate the x2 values and store them. 2) now change into the new pmu mode. this will load the new switch conditions in the pmu circuitry and load the dac register with the stored x2 data. or 1) use the hi-z v or hi-z i mode in the pmu register, this makes the amplifier high impedance. 2) now load any dac x1 values that need to be loaded. remember that x1 registers are available per voltage and current range, so you can preload these and may not need to make changes. 3) when the hi-z (v or i) modes are used, the relevant dac outputs are automatically updated (fin, cll, clh dacs). for example, when selecting hi-z v (voltage), the fin voltage x2 result is loaded, offset and gain corrected, cached and loaded to the fin dac. when forcing a voltage, current clamps are engaged, so the cll i (current) register can be loaded, gain and offset corrected and loaded to the dac register. similarly, for the clh i register. 4) now change into the new pmu mode (fi/fv). this will load the new switch conditions in the pmu circuitry. as the dac outputs are already loaded, transients when changing current or voltage mode will be minimized.
preliminary technical data ad5522 rev. prm | page 43 of 48 required external components the minimum required external components are shown in the block diagram below. decoupling will be very dependent on the type of supplies used, other decoupling on the board and the noise in the system. it is possible more or less decoupling may be required as a result. dutgnd dut extmeasih3 extmeasil3 foh3 extfoh3 av ss av dd c comp(0-3) vref up to 64ma dv cc measvh3 c ff3 ref a v ss av dd dv cc 0.1 f 0.1 f 0.1 f dut extmeasih2 extmeasil2 foh2 extfoh2 up to 64ma measvh2 c ff2 dut extmeasih0 extmeasil0 foh0 extfoh0 up to 64ma measvh0 c ff0 dut extmeasih1 extmeasil1 foh1 extfoh1 up to 64ma measvh1 c ff1 10 f 10 f 10 f 0.1 f figure 28. external components required for use with this pmu device.
ad5522 preliminary technical data rev. prm | page 44 of 48 power supply decoupling in any circuit where accura cy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5522 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5522 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (av ss , av dd , v cc ), it is recommended to tie these pins to gether and to decouple each supply once. the ad5522 should have ample supply decoupling of 10 f in parallel with 0.1 f on each su pply located as close to the package as possible, ideally right up against the device. the 10f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effect ive series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impeda nce path to ground at high frequencies, to handle transient currents due to internal logic switching. digital lines running under the device should be avoided, because these couple noise onto the device. the analog ground plane should be allowed to run under the ad5522 to avoid noise coupling (only with the package with paddle up).. the power supply lines of the ad5522 should use as large a trace as possible to provide low impedanc e paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. it is essential to minimize noise on all v ref lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces th e effects of feedthrough through the board. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. also note that the exposed padd le of the ad5522 is connected to the negative supply av ss .
preliminary technical data ad5522 rev. prm | page 45 of 48 typical application for the ad5522 figure 29 shows the ad5522 as used in an ate system. this device can used as a per pin parametric unit in order to speed up the rate at which testing can be done. the central pmu shown in the block diagram is usually a highly accurate pmu, and is shared among a number of pins in the tester. in general, many discrete levels are required in an ate system for the pin drivers, comparators, clamps, and active loads. dac devices, such as the ad5379, offer a highly integrated solution for a number of these levels. the ad5379 is a dense 40-channel dac designed with high channel requirements, such as ate . comp driver driver ppmu active load dut formatter de-skew timing generator dll,logic compare memory compare memory vh vl vth vtl iol ioh vcom relays 50 ? coax vch vcl vterm gnd sense timing data memory timing data memory formatter de-skew central pmu dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac dac adc adc adc dac dac adc adc guard amp guard amp driven shield device power supply ad5522 figure 29. typical applications circuit using the ad5522 as a per pin parametric unit.
ad5522 preliminary technical data rev. prm | page 46 of 48 outline dimensions compliant to jedec standards ms-026-add-hd 0.27 0.22 0.17 1 20 21 40 40 61 80 60 41 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 20 21 61 80 60 41 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 9.50 bsc sq bottom view (pins up) exposed pad figure 30. 80 lead tqfp/e p with exposed pad on bottom compliant to jedec standards ms-026-add-hu 0.27 0.22 0.17 1 20 21 40 40 61 80 60 41 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 20 21 61 80 60 41 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 6.50 bsc 9.50 bsc bottom view (pins up) exposed pad figure 31. 80 lead tqfp/e p with exposed pad on top
preliminary technical data ad5522 rev. prm | page 47 of 48 ordering guide model function package description 1 package options ad5522jsvd quad pmu with 4 internal current ranges, full comparator function, 1 external current range, spi and lvds serial interfaces. 80 lead tqfp with exposed pad on bottom sv-80 ad5522jsvuz 2 quad pmu with 4 internal current ranges, full comparator function, 1 external current range, spi and lvds serial interfaces. 80 lead tqfp with expos ed pad on top sv-80 ad5523jcpz 2,3 quad pmu, 4 internal current ranges, window comparator function, spi interface. 64 lead lfcsp with exposed pad on bottom 9mm x 9mm cp-64 1 exposed pad is electrically connected internally to av ss. 2 lead free package. 3 reduced functionality. contact factory for ad5523 datasheet and more details.
ad5522 preliminary technical data rev. prm | page 48 of 48 notes ? 2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective companies. printed in the u.s.a. pr06197-0-03/07(prm)

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